The present invention relates to a circuit configuration with a first and a second signal line for serially transmitting a number of a plurality of bit groups.
Integrated circuits generally have signal lines which are used for serially transmitting individual bit groups, for example in the form of data words or command words. In general, different logic states 0 and 1 are transmitted, these having different voltage levels. The logic state 0 corresponds to a voltage of 0V, for example, and the logic state 1 corresponds to a voltage of 2.5V, for example. When information is transmitted over electrical lines using different voltage levels, electric current is drawn. The particular reason for this is that the signal lines have electrical capacitances whose charges need to be reversed when there is a change of signal state. Particularly in circuit configurations in which a plurality of integrated circuits, for example on a xe2x80x9cmotherboardxe2x80x9d, are connected to one another by a system bus, comparatively high line capacitances are present. In this case, the respective output drivers in the circuits need to reverse the charges of the line capacitances of the system bus during signal transmission.
Assuming that the load on an output driver of the circuit is purely capacitive, that is to say that the current drawn is used primarily for reversing the charges of the line capacitances (leakage currents being ignored), the current drawn can be calculated as:
I=kxc2x7nxc2x7Cxc2x7Vxc2x7F.
In this context, V denotes the voltage for an output driver, I denotes the current drawn, C denotes the capacitance whose charge is to be reversed, F denotes the system frequency, n denotes the number of output drivers and k denotes a constant which is dependent on the bit patterns which are to be transmitted.
If, by way of example, bit groups containing 8 bits each are transmitted serially, then a maximum current drawn for signal transmission is reached when, upon serial transmission of the bit groups, the respective bits corresponding to one another each change their signal state upon transmission of a respective bit group. One possible series of patterns is, by way of example, 00000000, 11111111, 00000000, etc. In this case, the current drawn is governed primarily by the signal transitions from 0 to 1. Upon transmission of the first two bit groups cited, eight signal state changes from 0 to 1 occur. In the example cited, only two bit patterns are used. To calculate a proportionality factor for calculating a current drawn, the eight signal state changes are divided by two (number of bit patterns), and a proportionality factor of 4 is obtained. By contrast, an average current drawn gives a proportionality factor of 2 if it is assumed that, when a bit with the signal state 0 is transmitted, the likelihood of subsequent transmission of a bit with the signal state 1 is 50%. Accordingly, the average current drawn is halved as compared with the maximum current drawn that is cited above.
It is accordingly an object of the invention to provide a circuit configuration with signal lines for serially transmitting a plurality of bit groups that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which permits the lowest possible current drawn for signal transmission.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration. The circuit configuration contains a first signal line and a second signal line for serially transmitting a number of a plurality of bit groups, a transmission unit connected to the first signal line, a third signal line, a control line, and a receiver unit connected to the second signal line and coupled to the transmission unit through the third signal line and the control line. The transmission unit receives a received first bit group to be transmitted and a subsequent, received second bit group to be transmitted and respectively transmits the received first bit group and the received second bit group to the receiver unit in an unaltered or an altered form resulting in a transmitted first bit group and a transmitted second bit group. The transmission unit respectively identifies a signal state change between bits in the transmitted first bit group and corresponding bits in the received second bit group and determines a number of signal state changes. The transmission unit transmits the received second bit group to the receiver unit in an unaltered or an altered form on a basis of the number of signal state changes, with altered transmission being indicated by a control signal on the control line.
The inventive circuit configuration contains the transmission unit which is connected to the first signal line and also the receiver unit which is connected to the second signal line. The transmission unit and the receiver unit are coupled to one another via the third signal line and the control line. To transmit the serial bit groups, the transmission unit receives a first bit group that is to be transmitted and a subsequent, second bit group that is to be transmitted. It respectively transmits the bit groups to the receiver unit in unaltered or altered form. The transmission unit respectively identifies a signal state change between bits in the transmitted first bit group and corresponding bits in the received second bit group and establishes a number of signal state changes. On the basis of the number of signal state changes, the second bit group is transmitted to the receiver unit by the transmission unit in unaltered or altered form, with altered transmission being indicated by a control signal on the control line. The control signal indicates to the receiver unit if the second bit group is transmitted by the transmission unit in altered form. This allows the receiver unit to decode the altered bit group transmitted by the transmission unit and to return it to its initial state.
The inventive circuit configuration makes it possible to minimize the charge reversal operations during signal transmission between two circuits and hence to minimize the current drawn for signal transmission. By way of example, a first circuit has the transmission unit, and a second circuit has the receiver unit. Both circuits are connected via the third signal line, which is in the form of a system bus, for example. Signal transmission between the transmission unit and the receiver unit is controlled on the basis of the number of signal state changes between mutually corresponding bits in the respective bit groups. Since, as described in the introduction, the type and number of signal state changes affect the current drawn during signal transmission, the current drawn during signal transmission can be minimized in this way.
In one embodiment of the invention, the transmission unit establishes the number of signal state changes from 0 to 1 between the bits in the transmitted first bit group and the corresponding bits in the received second bit group. Advantageously, the second bit group is transmitted to the receiver unit by the transmission unit in altered form if the number of signal state changes from 0 to 1 is greater than the number of common corresponding bits in the transmitted first and the received second bit group with the state 0. In particular, the bits in the second bit group that are received by the transmission unit are in this case transmitted to the receiver unit in inverted form for the purpose of altered transmission. This allows the signal state changes from 0 to 1 which govern the current drawn to be reduced and hence allows the current drawn for transmission via the third signal line to be reduced.
In accordance with an added feature of the invention, the transmission unit transmits the second bit group to the receiver unit in unaltered form if the number of signal state changes from 0 to 1 is less than or equal to the number of common corresponding bits in the transmitted first bit group and the received second bit group with the state 0.
In accordance with a further feature of the invention, a first chip is provided. The transmission unit is disposed on the first chip. In addition, a second chip is provided, and the receiver unit is disposed on the second chip, the third signal line connecting the first chip to the second chip.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration with signal lines for serially transmitting a plurality of bit groups, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.